MPC8280 datasheet(1045/1386 Pages) FREESCALE

1045 / 1386 page

ATM Controller and AAL0, AAL1, and AAL5

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

31-85

Modes are selected through GFMR[DIAG], as shown in Table 31-46.

31.12.3 Extended Number of PHYs

The MPC8280 has additional pin muxing to support 31 PHYs on both FCC1 and FCC2. To utilize this

feature, do the following:

•

Program CMXUAR[MAD4] = 1

•

Program CMXUAR[MAD3] = 1

•

Select dedicated UTOPIA address lines for FCC2 in the parallel I/O (TxADDR[4:3],

RxADDR[4:3]).

Refer to Chapter 41, “Parallel I/O Ports,” of this document and Section 16.4.1, “CMX UTOPIA Address

31.13 ATM Registers

The following sections describe the configuration of the registers in ATM mode.

31.13.1 General FCC Mode Register (GFMR)

The GFMR mode field should be programmed for ATM mode. To enable transmit and receive functions,

ENT and ENR must be set as the last step in the initialization process. Full GFMR details are given in

Section 30.2, “General FCC Mode Registers (GFMRx).”

31.13.2 FCC Protocol-Specific Mode Register (FPSMR)

The FCC protocol-specific mode register (FPSMR), shown in Figure 31-59, controls various

protocol-specific FCC functions. The user should initialize the FPSMR. Erratic behavior may result if

there is an attempt to write to the FPSMR while the transmitter and receiver are enabled.

Table 31-46. UTOPIA Loop-Back Modes

DIAG

Description

Normal mode

Loop-back. UTOPIA Rx and Tx signals are shorted internally. Output pins are driven, input pins are ignored.

Reserved

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