MPC8280 datasheet(1088/1386 Pages) FREESCALE

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ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

32-28

Freescale Semiconductor

0x02

0–3

—

Internal use only. Initialize to 0.

4–10

—

Internal use only. Initialize to 0.

CASM

Common associated signaling mode.

CAS operation mode is disable.

1 CAS operation mode is enable.

—

Reserved, should be cleared during initialization.

13–15

AAL

AAL type

000 AAL0 —Reassembly with no adaptation layer

001 AAL1 —ATM adaptation layer 1

010 AAL5 —ATM adaptation layer 5

100 AAL2 —ATM adaptation layer 2. Refer to Chapter 33, “ATM AAL2.”

101 AAL1_CES —ATM adaptation layer 1 with circuit emulation service

All others reserved.

0x04

—

RxDBPTR

Receive data buffer pointer. Holds real address of current position in the Rx buffer.

0x08

—

Cell Time

Stamp

Used for reassembly time-out. Whenever a cell is received, the MPC8280 time stamp

timer is sampled and written to this field. See Section 14.3.8, “RISC Time-Stamp

Control Register (RTSCR).”

0x0C

—

RBD_Offset RxBD offset from RBD_BASE. Points to the channel’s current BD. User-initialized to 0;

updated by the CP.

0x0E-0

x18

—

Protocol-specific area.

0x1A

—

MRBLR

Maximum receive buffer length. Used in both static and dynamic buffer allocation.

Note that in CES mode (CESM=1) this value must be a multiple of 8 (MCC limited).

0x1C

0–1

—

Reserved, should be cleared during initialization.

2–7

PMT

Performance monitoring table. Points to one of the available 64 performance

monitoring tables. The starting address of the table is PMT_BASE+PMT

× 32. Can be

changed on-the-fly.

8–15

RBD_BASE RxBD base. Points to the first BD in the channel’s RxBD table. The 8 most-significant

bits of the address are taken from BD_BASE_EXT in the parameter RAM. The four

least-significant bits of the address are taken as zeros.

0x1E

0–11

CCASM

Core CAS modify. When this mode is enabled, the CP sets OCASSR[MCASB

n] sticky

bit each time the outgoing (ATM to TDM) CAS block is changed.

Core CAS modify mode is disabled.

1 Core CAS modify mode is enabled.

See Section 32.10, “Outgoing CAS Status Register (OCASSR).”

CESM

Circuit Emulation Service Mode.

CES operation mode is disable. Adaptive Slip control mechanism is disabled.

1 CES operation mode is enable. Adaptive Slip control mechanism is enabled.

—

Reserved, should be cleared during initialization.

Performance monitoring. Can be changed on-the-fly.

0 No performance monitoring for this VC.

1 Perform performance monitoring for this VC. Whenever a cell is received for this VC

the performance monitoring table that its code is written in the PMT field is updated.

Table 32-5. RCT Field Descriptions (continued)

Offset

Bits

Name

Description

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