MPC8280 datasheet(1101/1386 Pages) FREESCALE

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ATM AAL1 Circuit Emulation Service

MPC8280 PowerQUICC II Family Reference Manual, Rev. 1

Freescale Semiconductor

32-41

32.13 AAL1 CES Exceptions

There are four circular interrupt queues available for each channel. The interrupt queue number is

programmed in RCT[INTQ] and TCT[INTQ]. Events can be masked by clearing interrupt mask bits in the

RCT and TCT.

When one of the AAL1 channels generates an interrupt request, the CP writes a new entry to the table

consisting of the channel’s number and a description of the exception. The valid (V) bit is then set and

INTQ_PTR is incremented. When INTQ_PTR reaches the entry in which W is set, it returns to the first

entry of the queue. Each one-word entry provides detailed interrupt information to the host. More details

can be found in Section 29.11, “ATM Exceptions.”

32.13.1 AAL1 CES Interrupt Queue Entry

The figure below shows an interrupt queue entry.

The table below describes interrupt queue entry fields.

EOSF

End of super frame. CES mode (TCT[CESM=1]) only.

0 No signaling information should be inserted after closing this buffer.

1 When closing this buffer the ATM transmitter fetches the CAS information from the

internal CAS block and packs it to the outgoing AAL1 cells.

Note that this bit should be set by the user at the end of each super-frame in the

common (MCC, ATM) BD table. See Section 32.4.6, “Channel Associated Signaling

(CAS) Support.”

10–15

—

0x02

—

The number of octets the ATM controller should transmit from this BD’s buffer. It is not

modified by the CP. The value of DL should be greater than zero.

0x04

—

TXDBPTR Tx data buffer pointer. Points to the address of the associated buffer. The buffer may

reside in either internal or external memory. This value is not modified by the CP.

Offset + 0x00

—

SLIPE

SLIPS

CASUP

TBNR

RXF

BSY

TXB

RXB

Offset + 0x02

Channel Code (CC)

Figure 32-30. AAL1 CES Interrupt Queue Entry

Table 32-13. AAL1 CES Interrupt Queue Entry Field Descriptions

Offset

Bits

Name

Description

0x00

Valid interrupt entry

0 This interrupt queue entry is free and can be use by the CP.

1 This interrupt queue entry is valid. The host should read this interrupt and clear this

bit.

1—

—

Table 32-12. AAL1 CES TxBD Field Descriptions (continued)

Offset

Bits

Name

Description

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