This Data Sheet may be revised by subsequent versions

©2004 Eon Silicon Solution, Inc., www.essi.com.tw

or modifications due to changes in technical specifications.

6

EN25P32

Rev. C, Issue Date: 2007/10/18

26

64

1A0000h – 1AFFFFh

25

64

190000h – 19FFFFh

24

64

180000h – 18FFFFh

23

64

170000h – 17FFFFh

22

64

160000h – 16FFFFh

21

64

150000h – 15FFFFh

20

64

140000h – 14FFFFh

19

64

130000h – 13FFFFh

18

64

120000h – 12FFFFh

17

64

110000h – 11FFFFh

16

64

100000h – 10FFFFh

15

64

0F0000h – 0FFFFFh

14

64

0E0000h – 0EFFFFh

13

64

0D0000h – 0DFFFFh

12

64

0C0000h – 0CFFFFh

11

64

0B0000h – 0BFFFFh

10

64

0A0000h – 0AFFFFh

9

64

090000h – 09FFFFh

8

64

080000h – 08FFFFh

7

64

070000h – 07FFFFh

6

64

060000h – 06FFFFh

5

64

050000h – 05FFFFh

4

64

040000h – 04FFFFh

3

64

030000h – 03FFFFh

2

64

020000h – 02FFFFh

1

64

010000h – 01FFFFh

0

64

000000h – 00FFFFh

OPERATING FEATURES

SPI Modes

The EN25P32 is accessed through an SPI compatible bus consisting of four signals: Serial Clock (CLK),

Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Both SPI bus operation Modes 0

(0,0) and 3 (1,1) are supported. The primary difference between Mode 0 and Mode 3, as shown in Figure

3, concerns the normal state of the SCK signal when the SPI bus master is in standby and data is not

being transferred to the Serial Flash. For Mode 0 the SCK signal is normally low. For Mode 3 the SCK

signal is normally high. In either case data input on the DI pin is sampled on the rising edge of the SCK.

Data output on the DO pin is clocked out on the falling edge of SCK.