RT9232BGS datasheet(12/14 Pages) RICHTEK

12 / 14 page

RT9232B

DS9232B-03

March 2007

www.richtek.com

MOSFET Selection

The selection of MOSFETs is based upon the

considerations of RDS(ON), gate driving requirements, and

thermal management requirements. The power loss of

upper MOSFET consists of conduction loss and switching

loss and is expressed as :

where TRISE and TFALL are rising and falling time of VDS of

upper MOSFET respectively. RDS(ON) and QG should be

simultaneously considered to minimize power loss of upper

MOSFET.

The power loss of lower MOSFET consists of conduction

loss, reverse recovery loss of body diode, and conduction

loss of body diode and is expressed as :

where TDIODE is the conducting time of lower body diode.

Special control scheme is adopted to minimize body diode

conducting time. As a result, the RDS(ON) loss dominates

the power loss of lower MOSFET. Use MOSFET with

adequate RDS(ON) to minimize power loss and satisfy

thermal requirements.

Feedback Compensation

Figure 2 highlights the voltage-mode control loop for a

synchronous buck converter. Figure 3 shows the

corresponding Bode plot. The output voltage (VOUT) is

regulated to the reference voltage. The error amplifier EA

output (COMP) is compared with the oscillator (OSC)

sawtooth wave to provide a pulse-width modulated (PWM)

wave with an amplitude of VIN at the PHASE node. The

PWM wave is smoothed by the output filter (L and COUT).

The modulator transfer function is the small-signal transfer

function of VOUT/COMP. This function is dominated by a

DC gain and the output filter (L and COUT), with a double

pole break frequency at FP_LC and a zero at FZ_ESR. The

DC gain of the modulator is simply the input voltage (VIN)

divided by the peak-to-peak oscillator voltage

ΔV

OSC

(8)

The break frequency FLC and FESR are expressed as

Equation (10) and (11) respectively.

The compensation network consists of the error amplifier

EA and the impedance networks ZIN and ZFB. The goal of

the compensation network is to provide a closed loop

transfer function with the highest DC gain, the highest

0dB crossing frequency (FC) and adequate phase margin.

Typically, FC in range 1/5~1/10 of switching frequency is

adequate. The higher FC is, the faster dynamic response

is. A phase margin in the range of 45

°C~ 60°C is desirable.

The equations below relate the compensation network’s

poles, zeros and gain to the components (R1, R2, R3,

C1, C2, and C3) in Figure 2.

(12)

(13)

(14)

(15)

(10)

(11)

OSC

ΔV

OSC

Driver

REF

PWM

Comparator

E/A

REF

OUT

COMP

ESR

PHASE

OUT

Figure 2

OSC

FALL

RISE

OUT

DS(ON)

OUT

SW_UPPER

COND_UPPER

UPPER

)

OSC

DIODE

OUT

OSC

DS(ON)

OUT

DIODE

COND_LOWER

LOWER

(9)

OUT

Z_ESR

OUT

P_LC

ESR

)

(R1

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