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5 Not production tested in die form, characterized by chip design and tested in package.

.

High Speed CMOS Logic – 54HC74

Rev 1.0

21/11/17

Timing Requirements5

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

2.0

80

100

120

4.5

16

20

24

Minimum Setup

Time, D to CLK

(Figure 3)

tsu

6.0

CL = 50pF,

tr = tf = 6ns

14

17

20

ns

2.0

3.0

3.0

3.0

4.5

3.0

3.0

3.0

Minimum Hold Time,

CLK to D

(Figure 3)

th

6.0

CL = 50pF,

tr = tf = 6ns

3.0

3.0

3.0

ns

2.0

8.0

8.0

8.0

4.5

8.0

8.0

8.0

Minimum Recovery

Time, PRE or CLR

Inactive to CLK

(Figure 2)

trec

6.0

CL = 50pF,

tr = tf = 6ns

8.0

8.0

8.0

ns

2.0

60

75

90

4.5

12

15

18

Minimum Pulse

Width, CLK

(Figure 1)

tw

6.0

CL = 50pF,

tr = tf = 6ns

10

13

15

ns

2.0

60

75

90

4.5

12

15

18

Minimum Pulse

Width, PRE or CLR

(Figure 2)

tw

6.0

CL = 50pF,

tr = tf = 6ns

10

13

15

ns

2.0

1000

1000

1000

4.5

500

500

500

Maximum Input Rise

and Fall Times

(Figure 1)

tr, tf

6.0

CL = 50pF,

tr = tf = 6ns

400

400

400

ns

 

Switching Waveforms

Figure 1 – Data, Clock and Output

Figure 2 – Set, Reset, Clock and Output