Advanced CMOS TTL Input – 74ACT574

DC Electrical Characteristics Continued (Voltages Referenced to GND)

Rev 1.0

19/3/2021

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

FULL RANGE

4

UNITS

85°C

4.5V

0.1

0.1

0.1

5.5V

IOUT = 50µA

0.1

0.1

0.1

V

4.5V

0.36

0.44

0.44

Maximum Low-Level

Output Voltage

VOL

VIN = VIL or VIH

5

IOL = 24mA

0.36

0.44

5.5V

0.44

V

Maximum Input

Leakage Current

IIN

5.5V

VIN = VCC or GND

±0.1

±1.0

±1.0

µA

Maximum 3-State

leakage current

IOZ

5.5V

VOUT=VCC or GND

VIN = VIL or VIH

±0.5

±2.5

±2.5

µA

Additional Maximum

ICC / Input

ΔICCT

5.5V

VIN = VCC -2.1V

1

1.5

1.5

mA

IOLD

5.5V

VOLD = 1.65V Max

-

75

75

Minimum Dynamic

Output Current

6

IOHD

5.5V

VOHD = 3.85V Min

mA

-

-75

-75

Maximum Quiescent

Supply Leakage

Current

ICC

5.5V

VIN = VCC or GND

IOUT = 0µA

8

80

80

µA

5. All outputs loaded; thresholds on input associated with output under test. 6. Maximum test duration 2.0 ms, one output loaded at a time.

AC Electrical Characteristics7

LIMITS

PARAMETER

SYMBOL

VCC

CONDITIONS

25°C

85°C

FULL RANGE

4

UNITS

Maximum Clock

Frequency

CL = 50pF,

Input tf =tr= 3ns

fmax

5V ±0.5

100

85

85

MHz

tPLH

11

12

12

Propagation Delay

CLK to Q

(Figure 1,5)

tPHL

5V ±0.5

CL = 50pF,

ns

Input tf =tr= 3ns

10

11

11

tPZH

9.5

10

10

Output Enable Time

CL = 50pF,

OE to Q

(Figure 3,6)

tPZL

5V ±0.5

ns

Input tf =tr= 3ns

9.0

10

10

tPHZ

10.5

11.5

11.5

Output Enable Time

OE to Q

CL = 50pF,

ns

5V ±0.5

Input tf =tr= 3ns

(Figure 3,6)

tPLZ

8.5

9.0

9.0

Maximum Input

CL = 50pF,

Capacitance

CIN

5V ±0.5

Input tf =tr= 3ns

10

10

10

pF

TYPICAL

Power Dissipation

TJ = 25°C,

pF

Capacitance

7

CPD

-

VCC =5.0V

40

7. Not production tested in die form, characterized by chip design.

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