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High Speed CMOS Logic – 74HC123

Rev 1.0

06/10/19

COORDINATES (mm)

PAD

FUNCTION

X

Y

1

1A

0.155

0.525

2

1B

0.155

0.175

3

1R

0.680

0.170

4

1Q

0.815

0.135

5

2Q

1.060

0.130

6

2CX

1.305

0.130

7

2RXCX

1.625

0.135

8

GND

1.625

0.395

9

2A

1.625

0.595

10

2B

1.625

0.955

11

2R

1.165

0.955

12

2Q

0.965

0.995

13

1Q

0.770

0.995

14

1CX

0.415

0.995

15

1RXCX

0.145

0.995

16

VCC

0.155

0.730

CONNECT CHIP BACK TO VCC OR FLOAT

Pad Layout and Functions

Logic Diagram

1900 (74.80 mils)

0,0

Pad 14 = VCC

Pad 7 = GND

Function Table

INPUTS

OUTPUTS

A

B

R

Q

Q

FUNCTION

↓

H

H

OUTPUT ENABLE

X

L

H

L*

H*

INHIBIT

H

X

H

L*

H*

INHIBIT

L

↑

H

OUTPUT ENABLE

L

H

↑

OUTPUT ENABLE

X

X

L

L

H

INHIBIT

H = High level, L = Low level , X = Don’t care,

↑ = High-to-low transition, ↓= Low-to-high transition

= x1 high level output pulse,

= x1 low level output pulse

* If the monostable was triggered before this condition,

pulse will continue as programmed.

9

8

7

6

5

4

3

2

1

16

15

14

13

12

11

DIE ID

10