Overvoltage-Protection Controllers with

Status

FLAG

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7

Applications Information

MOSFET Configuration

The MAX4838A/MAX4840A/MAX4842A can be used

with either a single MOSFET configuration as shown in

the Typical Operating Circuit, or can be configured with

a back-to-back MOSFET as shown in Figure 7. The

back-to-back configuration has almost zero reverse

current when the input supply is below the output.

If reverse current leakage is not a concern, a single

MOSFET can be used. This approach has half the loss

of the back-to-back configuration when used with simi-

lar MOSFET types, and is a lower cost solution. Note

that if the input is actually pulled low, the output is

pulled low as well due to the parasitic body diode in the

MOSFET. If this is a concern, then the back-to-back

configuration should be used.

MOSFET Selection

The MAX4838A/MAX4840A/MAX4842A are designed for

use with either a single n-channel MOSFET or dual back-

to-back n-channel MOSFETs. In most situations,

well. If the input supply is near the UVLO maximum of

3.5V, consider using a MOSFET specified for a lower

FET to withstand the full 28V IN range of all devices.

Table 1 shows a selection of MOSFETs appropriate for

use with the MAX4838A/MAX4840A/MAX4842A.

IN Bypass Considerations

For most applications, bypass IN to GND with a 1µF

ceramic capacitor. If the power source has significant

inductance due to long lead length, take care to pre-

vent overshoots due to the LC tank circuit and provide

protection if necessary to prevent exceeding the 30V

absolute maximum rating on IN.

The MAX4838A/MAX4840A/MAX4842A provide protec-

tion against voltage faults up to 28V, but this does not

include negative voltages. If negative voltages are a con-

cern, connect a Schottky diode from IN to GND to clamp

negative input voltages.

ESD Test Conditions

ESD performance depends on a number of conditions.

The MAX4838A/MAX4840A/MAX4842A are specified

for ±15kV typical ESD resistance on IN when IN is

bypassed to ground with a 1µF ceramic capacitor.

Contact Maxim for a reliability report that documents

test setup, methodology, and results.

Human Body Model

Figure 8 shows the Human Body Model, and Figure 9

shows the current waveform it generates when dis-

charged into a low impedance. This model consists of

a 100pF capacitor charged to the ESD voltage of inter-

est, which is then discharged into the device through a

1.5k

Ω resistor.

TIMER STARTS

COUNTING

t = 50ms

t = 50ms

STANDBY

GATE = 0

FLAG = LOW

OVLO CHECK

GATE = 0

FLAG = LOW

STARTUP

GATE DRIVEN HIGH

FLAG = LOW

ON

GATE HIGH

FLAG = HIGH

Figure 6. State Diagram

MAX4838A

MAX4840A

MAX4842A

INPUT

0 TO 28V

IN

EN

GATE

FLAG

GND

1

6

4

2

3

OUTPUT

NMOS

1

µF

NOTE: EN AND PULLUP

RESISTOR ON MAX4838A/

MAX4840A/MAX4842A ONLY.

Figure 7. Back-to-Back External MOSFET Configuration