TPIC5403

4-CHANNEL INDEPENDENT GATE-PROTECTED

POWER DMOS ARRAY

SLIS038A – SEPTEMBER 1994 – REVISED SEPTEMBER 1995

4

POST OFFICE BOX 655303

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

td(on)

Turn-on delay time

32

55

td(off)

Turn-off delay time

VDD = 25 V,

RL = 20 Ω,tr1 = 10 ns,

27

50

ns

tr2

Rise time

DD

,

tf1 = 10 ns,

L

,

See Figure 2

r1

,

14

30

ns

tf2

Fall time

7

15

Qg

Total gate charge

V48 V

I

1 125 A

V10 V

6.6

8

Qgs(th) Threshold gate-to-source charge

VDS = 48 V,

See Figure 3

ID = 1.125 A,

VGS = 10 V,

0.6

0.7

nC

Qgd

Gate-to-drain charge

See Figure 3

2.8

3.2

LD

Internal drain inductance

5

nH

LS

Internal source inductance

5

nH

Rg

Internal gate resistance

0.25

Ω

thermal resistance

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

R

θJA

Junction-to-ambient thermal resistance

See Notes 4 and 7

90

°C/W

R

θJB

Junction-to-board thermal resistance

See Notes 5 and 7

49

°C/W

R

θJP

Junction-to-pin thermal resistance

See Notes 6 and 7

28

°C/W

NOTES:

4. Package mounted on an FR4 printed-circuit board with no heatsink

5. Package mounted on a 24 inch2, 4-layer FR4 printed-circuit board

6. Package mounted in intimate contact with infinite heatsink

7. All outputs with equal power