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SIS3045 데이터시트(PDF) 3 Page - Silicon Supplies |
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SIS3045 데이터시트(HTML) 3 Page - Silicon Supplies |
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3 / 7 page ![]() Absolute Maximum Ratings PARAMETER SYMBOL Monolithic Transistor Array – SiS3045 Rev 1.1 20/10/17 VALUE UNIT Collector-to-Emitter Voltage VCEO 15 V Collector-to-Base Voltage VCBO 20 V Collector-to-Substrate Voltage (Note 1) VCIO 20 V Emitter-to-Base Voltage VEBO 5 V Collector Current IC 50 mA Maximum Power Dissipation (Any one transistor) PD 300 mW Operating Temperature Range - -55 to 125 °C Maximum Junction Temperature TJ 175 °C PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS DC Electrical Characteristics T A = 25°C unless otherwise stated Collector to Base Breakdown Voltage V(BR)CBO IC = 10μA, IE= 0 20 60 - V Collector to Emitter Breakdown Voltage V(BR)CEO IC = 1mA, IB = 0 15 24 - V Collector-to-Substrate Breakdown Voltage V(BR)CIO IC = 10μA, ICI = 0 20 60 - V Emitter to Base Breakdown Voltage V(BR)EBO IE = 10μA, IC= 0 5 7 - V Collector Cutoff Current ICBO VCB = 10V, IE = 0 - 0.002 40 nA Collector Cutoff Current (Figure 2) ICEO VCE = 10V, IB = 0 - FIG 2 0.5 µA IC = 10mA - 100 - - IC = 1mA 40 100 - - Forward Current Transfer Ratio (Static Beta) (Note 3) (Figure 3) hFE VCE =3V IC = 10µA - 54 - - Input Offset Current for Matched Pair Q1 and Q2. (Note 2) (Figure 4) |IIO1 - IIO2| VCE = 3V, IC = 1mA - 0.3 2 µA IE = 1mA - 0.715 - Base-to-Emitter Voltage (Note 2) (Figure 5) VBE VCE = 3V IE =10mA - 0.800 - V Magnitude of Input Offset Voltage for Differential Pair (Note 2) (Figures 5, 7) |VBE1 - VBE2| VCE = 3V, IC = 1mA - 0.45 5 mV Magnitude of Input Offset Voltage for Isolated Transistors. (Note 2) (Figures 5, 7) |VBE3 - VBE4| |VBE4 - VBE5| |VBE5 - VBE3| VCE = 3V, IC = 1mA - 0.45 5 mV Temperature Coefficient of Base-to- Emitter Voltage (Figure 6) ΔVBE ΔT VCE = 3V, IC = 1mA - -1.9 - mV/°C Collector-to-Emitter Saturation Voltage VCES IB = 1mA, IC = 10mA - 0.23 - V Temperature Coefficient: Magnitude of Input Offset Voltage (Figure 7) |ΔVIO| ΔT VCE = 3V, IC = 1mA - 1.1 - µV/°C Notes: 1. The collector of each transistor is isolated from the substrate by an integral diode. The substrate (Terminal 13) must be connected to the most negative point in the external circuit to maintain isolation between transistors and to provide for normal transistor action. 2. Actual forcing current is via the emitter for this test. Page 3 of 7 www.siliconsupplies.com |
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