MU9C8328A Ethernet Interface

Rev. 0.8 Draft

3

/WE (Write Enable, Input, TTL)

/WE determines the direction of data flow into or out of the

MU9C8328As processor interface. It also determines the

state of /W to the LANCAM when the processor is

accessing the MU9C8328As internal LANCAM registers.

If /WE is LOW, the data is written into the register selected

by the A(3–0) bus. If /WE is HIGH, then data is read out

of the register selected by the A(3–0) bus.

A(3–0) (Address Bus, Input, TTL)

A(3–0) select the internal register in the MU9C8328A

accessed by the host processor as shown in Table 1.

A(3–0) are latched by the falling edge of /AS. A(3) is

internally pulled down with a nominal 50K resistor to

maintain compatibility with the MU9C8328.

D(15–0) (Data Bus, I/O, Three-state TTL)

D(15–0) is the processor data bus into and out of the

MU9C8328A, and is demuxed to the internal registers as

selected by the A(2–0) bus. If the register selected is the

Control, Status or Op-Code register, when /WE is LOW,

D(15–0) is loaded on the second rising edge of SYSCLK

after both /AS and /CS are LOW. When /WE is HIGH, data

from the selected register is output to the D(15–0) bus on

the second rising edge of SYSLCK after both /AS and /CS

are LOW. For CAM access, the write or read operation is

completed when READY returns HIGH. If /CS is HIGH, or

if data is not being read out of the MU9C8328A, the output

buffers go to HIGH-Z. Internally pulled down with nominal

50K resistor.

READY (Ready, Output, Three-state, TTL)

When writing to the Control, Status, or Op-Code register,

READY goes LOW on the first rising edge of SYSCLK

after both /AS and /CS are LOW and returns HIGH on the

next rising edge of SYSCLK. For a read cycle from those

registers, READY may only show a negative-going spike

at the first rising edge of SYSCLK after both /AS and /CS

are LOW. The data will be valid before the next rising

edge of SYSCLK. When writing to the CAM registers,

READY will go LOW on the first rising edge of SYSCLK

after both /CS and /AS are LOW. READY returns HIGH

three SYSCLK cycles after. When reading from the CAM

registers, READY will return HIGH five SYSCLK cycles later.

PIN DESCRIPTIONS

Continued

Pinout Diagram

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

GND

VCC

VCC

SERCLK

/RESET

READY

/AS

/INT

/E

/CM

/W

/EC

/MF

/REJECT

SERDAT

D0

/FF

/CS

/WE

GND

/NETRDY

TEST 1

TEST 5

TEST 4

TEST 3

TEST 2

NTE ST OUT

NTEST_EN (Tie Low)

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

MU9C8328A-RDC

100-pin PQFP

(Top View)