전자부품 데이터시트 검색엔진
  Korean  ▼
ALLDATASHEET.CO.KR

X  

FXLS8971CFR1 데이터시트(PDF) 22 Page - NXP Semiconductors

부품명 FXLS8971CFR1
상세설명  3-Axis Low-g Accelerometer
PDF  100 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
Logo NXP - NXP Semiconductors

FXLS8971CFR1 데이터시트(HTML) 22 Page - NXP Semiconductors

Back Button FXLS8971CFR1 Datasheet HTML 18Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 19Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 20Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 21Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 22Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 23Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 24Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 25Page - NXP Semiconductors FXLS8971CFR1 Datasheet HTML 26Page - NXP Semiconductors Next Button
Zoom Inzoom in Zoom Outzoom out
 22 / 100 page
background image
NXP Semiconductors
FXLS8971CF
3-Axis Low-g Accelerometer
aaa-040844
tHCS
tSCLKL
tSCLKH
tSCLK
tSCS
tSET
tHOLD
tWCS
SPI_CS_B
SCLK
SPI_MOSI
SPI_MISO
tDDLY
tHZ
High-Impedance
High-Impedance
Figure 15. SPI timing diagram (4-wire mode)
13.6 SPI timing specifications (software enabled 3-wire mode)
Table 14 and Figure 16 specify and illustrate the minimum and maximum timing parameter values for correct
SPI interface functionality when FXLS8971CF is operated in 3-wire (software enabled) SPI mode. FXLS8971CF
only supports SPI mode '00', corresponding to CPOL = 0, and CPHA = 0. In this mode, the active state of the
clock is high and the idle state is low. Data is latched on the rising edge of the clock and propagated on the
falling edge. All timing specifications shown in Table 14 were determined under the following conditions: 10 pF
capacitor and 1 kΩ pull-up resistor present on all SPI signals, 105 °C, 1.8 V.
Note: When FXLS8971CF is operated in 3-wire SPI mode - by setting SENS_CONFIG1[SPI_M] = 1 - the
SA0/SPI_MISO pin is always placed in a high impedance (high-z) state, with the SPI_MISO pin output driver
disabled (tri-stated).
Specifications
Label
Description
Min.
Max.
Unit
fSCLK
SCLK frequency
0
4
MHz
tSCLK
SCLK Period
250
—
ns
tSCLKH
SCLK high time
100
—
ns
tSCLKL
SCLK low time
100
—
ns
tSCS
Setup time for SPI_CS_B signal
125
—
ns
tHCS
Hold time for SPI_CS_B signal
240
—
ns
tHZ
Hold time for SPI_DATA signal transition
back to high-impedance state
—
25
ns
tWCS
Inactive time for SPI_CS_B signal
600
—
ns
tSET
Data setup time for SPI_DATA signal
10
—
ns
tHOLD
Data hold time for SPI_DATA signal
10
—
ns
tDDLY
Data setup time for SPI_DATA signal (output
phase)
—
50
ns
Table 14.  Secondary timing values
FXLS8971CF
All information provided in this document is subject to legal disclaimers.
© 2024 NXP B.V. All rights reserved.
Product data sheet
Rev. 2.1 — 7 March 2024
22 / 100



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100


데이터시트 다운로드

Go To PDF Page


링크 URL



ALLDATASHEET 가 귀하에 도움이 되셨나요?  [ DONATE ] 

Alldatasheet는?   |   광고문의   |   운영자에게 연락하기   |   개인정보취급방침   |   링크 투 데이터시트    |   링크교환   |   제조사별 검색
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com