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PCAL9722HNMP 데이터시트(PDF) 13 Page - NXP Semiconductors

부품명 PCAL9722HNMP
상세설명  Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and reset
PDF  63 Pages
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제조업체  NXP [NXP Semiconductors]
홈페이지  http://www.nxp.com
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NXP Semiconductors
PCAL9722
Ultra low-voltage translating 22-bit SPI I/O expander with Agile I/O features, interrupt output and
reset
6.4.3 Polarity inversion registers (08h, 09h, 0Ah)
The Polarity inversion registers (registers 08h, 09h, 0Ah) allow polarity inversion of pins defined as inputs by
the Configuration register. If a bit in these registers is set (written with ‘1’), the corresponding port pin’s polarity
is inverted in the input register. If a bit in this register is cleared (written with a ‘0’), the corresponding port pin’s
polarity is retained. A register group write is described in Section 7.3 and a register group read is described in
Section 7.5.
Bit
7
6
5
4
3
2
1
0
Symbol
N0.7
N0.6
N0.5
N0.4
N0.3
N0.2
N0.1
N0.0
Default
0
0
0
0
0
0
0
0
Table 13. Polarity inversion port 0 register (address 08h)
Bit
7
6
5
4
3
2
1
0
Symbol
N1.7
N1.6
N1.5
N1.4
N1.3
N1.2
N1.1
N1.0
Default
0
0
0
0
0
0
0
0
Table 14. Polarity inversion port 1 register (address 09h)
Bit
7
6
5
4
3
2
1
0
Symbol
N2.7
N2.6
N2.5
N2.4
N2.3
N2.2
N2.1
N2.0
Default
0 (NA)
0 (NA)
0
0
0
0
0
0
Table 15. Polarity inversion port 2 register (address 0Ah)
6.4.4 Configuration registers (0Ch, 0Dh, 0Eh)
The Configuration registers (registers 0Ch, 0Dh, 0Eh) configure the direction of the I/O pins. If a bit in these
registers is set to 1, the corresponding port pin is enabled as a high-impedance input. If a bit in these registers
is cleared to 0, the corresponding port pin is enabled as an output. A register group write is described in
Section 7.3 and a register group read is described in Section 7.5.
Bit
7
6
5
4
3
2
1
0
Symbol
C0.7
C0.6
C0.5
C0.4
C0.3
C0.2
C0.1
C0.0
Default
1
1
1
1
1
1
1
1
Table 16. Configuration port 0 register (address 0Ch)
Bit
7
6
5
4
3
2
1
0
Symbol
C1.7
C1.6
C1.5
C1.4
C1.3
C1.2
C1.1
C1.0
Default
1
1
1
1
1
1
1
1
Table 17. Configuration port 1 register (address 0Dh)
PCAL9722
All information provided in this document is subject to legal disclaimers.
© 2023 NXP B.V. All rights reserved.
Product data sheet
Rev. 1.1 — 1 May 2023
13 / 63



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