74LVC2G86_5

© NXP B.V. 2007. All rights reserved.

Product data sheet

Rev. 05 — 7 September 2007

3 of 15

NXP Semiconductors

74LVC2G86

Dual 2-input EXCLUSIVE-OR gate

6.

Pinning information

6.1 Pinning

6.2 Pin description

Fig 4.

Pin configuration SOT505-2 (TSSOP8) and SOT765-1 (VSSOP8)

74LVC2G86

1A

1B

1Y

2Y

2B

GND

2A

001aab836

1

2

3

4

6

5

8

7

Fig 5.

Pin configuration SOT833-1 (XSON8)

Fig 6.

Pin configuration SOT902-1 (XQFN8)

74LVC2G86

2B

1Y

2A

2Y

1B

1A

GND

001aab837

36

27

18

45

Transparent top view

001aaf506

1B

2B

1A

2Y

1Y

2A

Transparent top view

3

6

1

5

7

2

terminal 1

index area

74LVC2G86

Table 3.

Pin description

Symbol

Pin

Description

SOT505-2, SOT765-1,

SOT833-1

SOT902-1

1A

1

7

data input

1B

2

6

data input

2Y

3

5

data output

GND

4

4

ground (0 V)

2A

5

3

data input

2B

6

2

data input

1Y

7

1

data output

8

8

supply voltage