IIS2DULPX datasheet(64/106 Pages) STMICROELECTRONICS

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8.53

TAP_CFG5 (74h)

R/W

Table 129. TAP_CFG5 register

TRIPLE_

TAP_EN

DOUBLE_

TAP_EN

SINGLE_

TAP_EN

REBOUND_

Table 130. TAP_CFG5 register description

TRIPLE_TAP_EN

This bit enables the triple-tap event. Default value: 0

(0: disabled; 1: enabled)

DOUBLE_TAP_EN

This bit enables the double-tap event. Default value: 0

(0: disabled; 1: enabled)

SINGLE_TAP_EN

This bit enables the single-tap event. Default value: 0

(0: disabled; 1: enabled)

REBOUND_T[4:0]

These bits program the number of samples to wait for the rebound to finish. The default value of these

bits is 00000b which means that the rebound logic is disabled. If the REBOUND_T[4:0] bits are set to a

different value, 1LSB corresponds to 2 samples (maximum 62 samples).

8.54

TAP_CFG6 (75h)

R/W

Table 131. TAP_CFG6 register

PRE_STILL_

ST3

PRE_STILL_

ST2

PRE_STILL_

ST1

PRE_STILL_

ST0

PRE_STILL_

Table 132. TAP_CFG6 register description

PRE_STILL_ST[3:0]

Selection of starting sample for stationary condition before shock (from the oldest sample in a buffer of

14 samples). 1 LSB = 1 sample (0: 1st sample, 13: 14th sample, maximum value is 13)

PRE_STILL_N[3:0]

Selection of number of samples for stationary condition before shock. 1 LSB = 1 sample (maximum 14

samples). If this field is set to 0, the stationary condition before shock is disabled.

IIS2DULPX

DS14580 - Rev 1

page 64/106

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