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SM5921AF 데이터시트(PDF) 13 Page - Nippon Precision Circuits Inc

부품명 SM5921AF
상세설명  8-channel Lip Sync Delay
PDF  27 Pages
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제조업체  NPC [Nippon Precision Circuits Inc]
홈페이지  http://www.npc.co.jp/en
Logo NPC - Nippon Precision Circuits Inc

SM5921AF 데이터시트(HTML) 13 Page - Nippon Precision Circuits Inc

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SM5921A
SEIKO NPC CORPORATION —13
Output Enable (OEN pin)
The SM5921A has an output enable control for the DOA, DOB, DOC, DOD outputs. When OEN is HIGH, the
output pins are disabled. The OEN pin has a pull-down resistor built-in. When the OEN pin is open-circuit (or
LOW), the output pins are enabled and delay data is output. The OEN pin is detected on the WCKI boundary
edge, which means that there is a maximum 1-word delay before the change is reflected at the output.
Direct Mute (DMUTEN pin)
Direct mute ON/OFF
Other mute operations
The outputs are also muted (direct mute) when a reset pulse is applied.
The outputs are also muted (direct mute) when the INIT flag is set.
The outputs are also muted (direct mute) when the PDW flag is set.
The outputs are also muted (direct mute) setting the delay data values.
DMUTEN
Function
LOW
0 data output from the next output word after writing the setting.
HIGH
Normal delay data output from the next output word after writing the setting.
RSTN
Function
LOW
0 data output from the next output word after writing the setting.
HIGH
Normal delay data output after 64 output words after writing the setting.
INIT
Function
LOW
Normal output operation.
HIGH
Normal delay data output after a 64-word mute interval after writing the setting.
PDW
Function
LOW (HIGH
→ LOW)
0 data output from the next output word after writing to the register. The outputs are muted during the interval until the
initialization data write point, and then mute is released for delay data output.
HIGH
0 data output from the next output word after writing data to the register.
Delay setting
Function
Intrinsic delay
0 data output from the next output word after writing to registers REG 0/H and 1/H. The outputs are muted during the
interval until the initialization data write point, and then mute is released for delay data output.
Individual delay
0 data output from the next output word after writing to registers REG 3/H to 9/H. The outputs are muted during the
interval until the initialization data write point, and then mute is released for delay data output.



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