SM5951A

SEIKO NPC CORPORATION —21

DSD Signal Delay Information and Adjustment

The DSD signal internal process flow is shown in the following diagram. Each stage of the process increases

the data delay, and the delay is adjusted internally so that the delay is approximately 1FS cycle.

Input-stage delay (I/O buffer)

The input processing delay due to DSD input format status and the BCKI/FS phase relationship is approxi-

mately 0.5 to 1.5 samples in length.

(1) Normal mode timing example

DSDIn_m

I/O

Buff

MIX

(1)

DSM

(16)

SW

(1)

FIR

Filter

(26)

DSM

(32)

Delay

Down

DSDOn

DSD64On

Delay = 58 (128fs sample)

Delay = 18 (DSD sample)

Delay 128

or

Delay 64

BCKI (MAX)

(Clocked)

nn + 2

n + 1

n

− 1

n + 1

n

BCKI (MAX)

BCKI (MIN)

DSDI (MIN)

Delay (MAX)

Delay (MIN)

BCKI (MIN)

(Clocked)

DSD buff1 (MAX)

(Input block)

DSD buff1 (MIN)

(Input block)

n

− 1

n + 1

n

n

− 2

DSD buff2 [Ch8:Ch1]

(Input block)

(ENFS)

CLK (1024fs)

BCKO

DSD input

(edit block)

CH1 CH2 CH3 CH4 CH5

CH6 CH7 CH8

CH1 CH2 CH3 CH4 CH5 CH6 CH7

COEF input

(edit block)

n

− 1

n

n + 1

DSDI (MAX)

CH8

CH1 CH2 CH3 CH4 CH5 CH6

CH7

CH8

CH1 CH2 CH3 CH4 CH5 CH6 CH7 CH8

n + 1

n + 1