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SM6801AB 데이터시트(PDF) 2 Page - Nippon Precision Circuits Inc |
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SM6801AB 데이터시트(HTML) 2 Page - Nippon Precision Circuits Inc |
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2 / 16 page ![]() SM6801A SEIKO NPC CORPORATION —2 BLOCK DIAGRAM PIN DESCRIPTION Number Name*1 *1. VDDS = VDD1, VDD2, VDDP = VDD3, VDD4, VSS = VSS1, VSS2 I/O*2 *2. Ip = input pin with built-in pull-up resistor Function 1 DRCN I Dynamic range compression mode setting (HIGH: normal operation, LOW: DRC mode) 2 VDD1 – Supply (input system) 3 VREF1 – Reference voltage 1 (bias voltage) 4 IN I Signal input 5 EQP I Equalizer network connection 6 EQN I Equalizer network connection 7 VSS1 – Ground (input system) 8 TESTN Ip Test pin (HIGH: normal operation, LOW: test mode) 9 VDD3 I Supply (OUTN stage) 10 OUTN O Speaker minus (–) output 11 VSS2 – Ground (output stage) 12 OUTP O Speaker plus ( +) output 13 VDD4 – Supply (OUTP stage) 14 PDWN I Power-down control (active LOW) 15 VDD2 – Supply (logic system) 16 MUTEN I Mute control (active LOW) IN VSS2 VSS1 OUTN VDD3 VDD1 PWM Modulator OSC EQP EQN + − MUTE, POWER DOWN, PROTECTION LEVEL SHIFTER OUTP BUFFER BUFFER LEVEL SHIFTER + − BIAS VREF VREF1 VDD2 DRCN PDWN MUTEN TESTN VDD4 |
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