Introduction

STCF03

18/35

7.11

Reading from a single register

The reading operation starts with a START bit followed by the 7 bit device address of

the address + R/W bit by an acknowledge pulse. The address of the register which should

be read is sent afterwards and confirmed again by an acknowledge pulse of STCF03 again.

Then the master generates a START bit again and sends the device address followed by the

R/W bit, which is 1 now. STCF03 confirms the receiving of the address + R/W bit by an

acknowledge pulse and starts to send the data to the master. No acknowledge pulse from

the master is required after receiving the data. Then the master generates a STOP bit to

terminate the communication. See Figure 10

7.12

Reading from multiple registers with incremental addressing

Reading from multiple registers starts in the same way like reading from a single register. As

soon as the first register is read, the register address is automatically increased. If the

master generates an acknowledge pulse after receiving the data from the first register, then

reading of the next register can start immediately without sending the device address and

Figure 9.

Writing to multiple register with incremental addressing

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

A

C

K

ADDRESS OF

REGISTER i

DATA i

A

C

K

A

C

K

S

T

O

P

M

S

B

M

S

B

L

S

B

L

S

B

DATA i+1

A

C

K

L

S

B

DATA i+2

A

C

K

L

S

B

DATA i+2

L

S

B

DATA i+n

A

C

K

M

S

B

M

S

B

M

S

B

M

S

B

M

S

B

A

C

K

L

S

B

SDA LINE

Figure 10.

Reading from a single register

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE

S

T

A

R

T

DEVICE

ADDRESS

7 bits

A

C

K

W

R

I

T

E

M

S

B

L

S

B

R

/

W

ADDRESS

OF

REGISTER

A

C

K

M

S

B

L

S

B

S

T

A

R

T

A

C

K

R

/

W

R

E

A

D

DEVICE

ADDRESS

7 bits

DATA

L

S

B

S

T

O

P

N

O

A

C

K

SDA LINE