TMPR4937 datasheet(92/552 Pages) TOSHIBA

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Chapter 5 Configuration Registers

5-12

Bit

Mnemonic

Field Name

Description

Initial Value Read/Write

SIO0CKD

SIO0 Clock

Disable

Controls clock pulses for the SIO0 controller.

0 = Supply clock pulses.

1 = Do not supply clock pulses.

R/W

SIO1CKD

SIO1 Clock

Disable

Controls clock pulses for the SIO1 controller.

0 = Supply clock pulses.

1 = Do not supply clock pulses.

R/W

15:11

⎯

Reserved

⎯

DMA1RST

DMAC1 Reset

Resets the DMAC controller 1.

0 = Normal state

1 = Reset

R/W

ACLRST

ACLC Reset

Resets the AC-link controller.

0 = Normal state

1 = Reset

Note: Reset the AC-link controller when it is not asserting the

interrupt and DMA request.

R/W

PIORST

PIO Reset

Resets the parallel IO controller.

0 = Normal state

1 = Reset

R/W

DMARST

DMAC Reset

Resets the DMA controller.

0 = Normal state

1 = Reset

R/W

PCICRST

PCIC Reset

Resets the PCI controller.

0 = Normal state

1 = Reset

R/W

⎯

Always set this bit to 1.

R/W

TM0RST

TMR0 Reset

Resets the TMR0 controller.

0 = Normal state

1 = Reset

R/W

TM1RST

TMR1 Reset

Resets the TMR1 controller.

0 = Normal state

1 = Reset

R/W

TM2RST

TMR2 Reset

Resets the TMR2 controller.

0 = Normal state

1 = Reset

R/W

SIO0RST

SIO0 Reset

Resets the SIO0 controller.

0 = Normal state

1 = Reset

R/W

SIO1RST

SIO1 Reset

Resets the SIO1 controller.

0 = Normal state

1 = Reset

R/W

Figure 5.2.5 Clock Control Register (2/2)

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