TMPR4937 datasheet(170/552 Pages) TOSHIBA

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Chapter 8 DMA Controller

8-14

Figure 8.3.3 Dual Address Burst Transfer (DMCCRn.USEXFSZ

= 1)

Figure 8.3.4 shows Dual Address Burst transfer when the Transfer Size Mode bit

(DMCCRn.USEXFSZ) is set to “0”, the lower 8 bits of the Transfer Start address for the transfer

source are set to 0xA8, the lower 8 bits of the Transfer Start address for the transfer destination are

set to (a) 0x28/(b) 0x30, and the Transfer Setting Size (DMCCRn.XFSZ) is set to 8 double words.

Panel (a) of this figure shows when the address offset is equivalent. In this case, first transfer of

three double words is performed up to the address that is aligned with the transfer setting size.

Then, transfer of eight double words that is specified by the transfer setting size is repeated.

On the other hand, panel (b) show when the address offset is not equivalent. In this case, first

only data up to the address that is aligned with the transfer setting size is read to the on-chip FIFO.

Then, data is written up to the address that is aligned with the transfer setting size as long as data

remains in the on-chip FIFO. Efficiency decreases since the transfer size is divided. Also, since

data may remain in the on-chip FIFO, Burst transfer of a Dual Address that uses the on-chip FIFO

simultaneously with another channel cannot be performed.

Using the Burst Inhibit bit makes it possible to mix Burst transfer with 8-Double-Word Single

transfer. This in turn makes it possible to perform Burst access only for memory access during

DMA transfer with external I/O devices that cannot perform Burst transfer.

When the Source Burst Inhibit bit (DMCCRn.SBINH) is set, data read from the Source Address

to the on-chip FIFO is divided into multiple 8-byte Single Read transfers, then transfer is

executed.

Source Address

FIFO (8 Double Words)

Destination Address

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