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TMPR4937 데이터시트(PDF) 182 Page - Toshiba Semiconductor

부품명 TMPR4937
상세설명  64-Bit TX System RISC TX49 Family
PDF  552 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

TMPR4937 데이터시트(HTML) 182 Page - Toshiba Semiconductor

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Chapter 8 DMA Controller
8-26
Bit
Mnemonic
Field Name
Description
Read/Write
6:3
FIFUM[3:0]
FIFO Use Enable
[3:0]
FIFO Use Enable [3:0] (Default: 0x0)
Each channel specifies whether to use 8-double word FIFO in Dual
Address transfer. FIFUM[n] corresponds to channel n.
Refer to “8.3.8.2 Burst Transfer During Dual Address Transfer” for more
information.
R/W
2
Reserved
⎯
1
RRPT
Round Robin
Priority
Round Robin Priority (Default: 0)
Specifies the method for determining priority among channels.
1: Round Robin method. Priority of the last channel used is the lowest,
and the next previous channel has the next lowest priority. Round robin
is in the order Channel 0 > Channel 1 > Channel > Channel 3.
0: Fixed Priority. Priority is fixed in the order Channel 0 > Channel 1 >
Channel 2 > Channel 3.
R/W
0
MSTEN
Master Enable
Master Enable (Default: 0)
This bit enables the DMA Controller.
1: Enable
0: Disable
Note: If the entire DMA Controller is disabled, then all internal logic
including the Bus Interface Logic and State Machine are reset.
R/W
Figure 8.4.1 DMA Master Control Register (2/2)



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