TMPR4937 datasheet(191/552 Pages) TOSHIBA

191 / 552 page

Chapter 8 DMA Controller

8-35

8.4.6

DMA Chain Address Register (DM0CHARn, DM1CHARn)

Offset Address: DMAC0 0xB000 (ch. 0) / 0xB040 (ch. 1) / 0xB080 (ch. 2) / 0xB0C0 (ch. 3)

DMAC1 0xB800 (ch. 0) / 0xB840 (ch. 1) / 0xB880 (ch. 2) / 0xB8C0 (ch. 3)

Reserved

: Type

: Initial value

Reserved

CHADDR[35:32]

R/W

: Type

⎯

: Initial value

CHADDR[31:16]

R/W

: Type

⎯

: Initial value

CHADDR[15:3]

Reserved

R/W

: Type

⎯

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

63:36

Reserved

⎯

35:3

CHADDR

Chain Address

Chain Address (Default: undefined)

When Chain DMA transfer is executed, this register sets the physical

address of the next DMA Command Descriptor to be read. If DMA transfer

according to the current Channel Register setting ends and the Chain

Enable bit (DMCCRn.CHNEN) is set, then the DMA Command Descriptor

is loaded in the Channel Register starting from the address indicated by

this register.

When a value other than “0” is set in this register, the Chain Enable bit

(DMCCRn.CHNEN) and the Transfer Active bit (DMCCRn.XFACT) are set.

When “0” is set in this register, only the Chain Enable bit

(DMCCRn.CHNEN) is cleared.

When the Chain Address field value reads a DMA Command Descriptor of

0, the value of this register is not updated and the value before that one

(address of the Data Command Descriptor when the value of the Chain

Address field being read was “0”) is held.

R/W

2:0

Reserved

R/W

Figure 8.4.6 DMA Chain Address Register

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