TMPR4937 datasheet(276/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-18

10.3.10.3 Dynamic Chain Operation

It is possible to dynamically add other DMA Command Descriptor Chains to a DMA Command

Descriptor Chain that is currently being processed when executing DMA data transfer. This is

done according to the following procedure.

DMA Command Descriptor Chain Construction

Constructs a DMA Command Descriptor Chain in memory.

Addition of DMA Command Descriptor Chains

Substitutes the address of the command descriptor that is at the beginning of the descriptor

chain to be added into the Descriptor Chain Address field at the end of the DMA Command

Descriptor Chain that is currently performing DMA transfer.

Chain Enable bit checking

Reads the value of the Chain Enable bit (CHNEN) in the PDMAC Configuration Register

(PDMCFG). If the read value is “0”, then the Chain Address field value of the DMA

Command Descriptor indicated by the address stored in the PDMAC Chain Address Register

(PDMCA) is written to the PDMAC Chain Address Register (PDMCA)

10.3.10.4 Data Transfer Size

The Transfer Size field (PDMCFG.XFERSIZE) of the PDMAC Configuration Register specifies

the transfer size of each G-Bus transaction in a DMA transfer. The transfer size can be selected

from one of the following: 1 DWORD, 1 QWORD, or 4 QWORD (Burst transfer).

1 QWORD or 4 QWORD can only be selected as the transfer size when the setting of the

PDMAC G-Bus Address Register (PDMGA) and the PDMAC PCI Bus Address Register

(PDMPA) is a 64-bit address boundary and the PDMAC Count Register (PDMCTR) setting is an

8-byte multiple. 1 DWORD must be selected as the transfer size in all other cases.

10.3.11 Error Detection, Interrupt Reporting

The PCI Controller reports the four following types of interrupts to the Interrupt Controller (IRC).

•

Normal Operation Interrupt

(Interrupt Number: 16, PCIC)

•

PDMAC Interrupt

(Interrupt Number: 15, PDMAC)

•

Power Management Interrupt

(Interrupt Number: 23, PCIPME)

•

Error Detection Interrupt

(Interrupt Number: 22, PCIERR)

When each cause is detected, an interrupt is reported if the corresponding Status bit is set, and the

corresponding Interrupt Enable Bit is set. The following tables list the name of each interrupt cause, the

Status bit, and the Interrupt Enable bit. Please refer to the explanation of each Status bit for more

information regarding each interrupt cause.

10.3.11.1 Normal Operation Interrupt

Name

Status Bit

Interrupt Enable Bit

M66EN Signal Assert Detect

P2GSTATUS

M66EN

P2GMASK

M66ENIE

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