TMPR4937 datasheet(291/552 Pages) TOSHIBA

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Chapter 10 PCI Controller

10-33

10.4.6 P2G Memory Space 0 PCI Upper Base Address Register (P2GM0PUBASE) 0xD014

This register is unused since the PCI Controller does not support the target dual-address cycle. It is

forbidden to write to this register.

10.4.7 P2G Memory Space 1 PCI Lower Base Address Register (P2GM1PLBASE) 0xD018

This register corresponds to the Memory Space 1 Lower Base Address Register at offset address 0x18

of the PCI Configuration Space.

This register cannot be accessed when the PCI Controller is in the Satellite mode.

BA[31:24]

Reserved

R/W

: Type

0x00

: Initial value

Reserved

TYPE

MSI

: Type

: Initial value

Bit

Mnemonic

Field Name

Description

Read/Write

31:24

BA[31:24]

Base Address

Base Address (Default: 0x00)

Sets the lower address of the PCI base address in Target Access Memory

Space 1. The size of Memory Space 1 is fixed at 16 MB.

R/W

23:4

Reserved

⎯

Prefetchable

Prefetchable (Fixed Value: 1)

1: Indicates that memory is prefetchable.

2:1

TYPE

Type

Memory Type (Default: 00)

00: Indicates that memory is placed in the 32-bit address space.

MSI

Memory Space

Memory Space Indicator (Fixed Value: 0)

0: Indicates that this Base Address Register is for use by the PCI Memory

Space.

Figure 10.4.6 P2G Memory Space 1 PCI Lower Base Address Register

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