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http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

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Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

PERFORMANCE

The following table gives a survey about

the Core area and performance in the

ALTERA® devices after Place & Route:

Device

Speed

grade

Logic Cells

CYCLONE

-6

2958

58 MHz

STRATIX

-5

2957

62 MHz

APEX II

-7

3092

50 MHz

APEX20KC

-7

2972

43 MHz

APEX20KE

-1

2972

39 MHz

ACEX1K

-1

3023

33 MHz

FLEX10KE

-1

3023

33 MHz

Core performance in ALTERA® devices

Area utilized by the each unit of DF6811 core

in vendor specific technologies is summarized

in table below.

Component

Area

[LC]

[FFs]

CPU*

1 986

284

Main Timer

180

50

COM/CAP

400

224

Watchdog

74

36

Pulse Acc.

44

19

SPI Interface

138

62

UART - SCI

272

129

I/O Ports

160

64

Total area

3 254

829

*CPU – consisted of ALU, Control Unit and Instruction Decoder, Bus

Controller with support for 16MB RAM, External IRQ and XIRQ pin

Interrupt Controller

Core components area utilization

IMPROVEM ENT

For user the most important is application

speed improvement. The most commonly

used arithmetic functions and theirs improve-

ment are shown in table below. Improvement

was computed as {M68HC11 clock periods}

divided by {DF6811 clock periods} required to

execute an identical function. More details are

available in core documentation

Function

Improve-

ment

8-bit addition (immediate data)

4

8-bit addition (direct addressing)

4

8-bit addition (indirect addressing)

4

8-bit subtraction (immediate data)

4

8-bit subtraction (direct addressing)

4

8-bit subtraction (indirect addressing)

4

16-bit addition (immediate data)

4

16-bit addition (direct addressing)

4

16-bit addition (indirect addressing

4

16-bit subtraction (immediate data)

4

16-bit subtraction (direct addressing)

4

16-bit subtraction (indirect addressing

4

Multiplication

10

Fractional division

14,9

Integer division

16.4

DF68XX FAMILY OVERVIEW

The main features of each DF68XX family member have been summarized in table below. It gives

a briefly member characterization helping user to select the most suitable IP Core for its application.

User can specify its own peripheral set (including listed below and the others) and requests the core

modifications.

Design

DF6805

4.1

64k

64k

-

7

7

-

-

*

2/2*

1*

*

4+

*

-

6 700

DF6808

3.2

64k

64k

-

7

7

-

-

*

2/2*

1*

*

4

*

-

8 900

DF6811

4.4

64k

16M

-

20

17

1*

*

5/3*

1*

*

4

*

*

*

12 000

DF6811CPU

4.4

64k

16M

-

3

3

+

1*

*

+

+

+

+

+

+

+

6 500

DF68XX family of High Performance Microcontroller Cores

+ optional

* configurable