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DF6811CPU 데이터시트(PDF) 6 Page - Digital Core Design

부품명 DF6811CPU
상세설명  8-bit FAST Microcontrollers Family
PDF  7 Pages
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제조업체  DCD [Digital Core Design]
홈페이지  http://www.digitalcoredesign.com
Logo DCD - Digital Core Design

DF6811CPU 데이터시트(HTML) 6 Page - Digital Core Design

  DF6811CPU Datasheet HTML 1Page - Digital Core Design DF6811CPU Datasheet HTML 2Page - Digital Core Design DF6811CPU Datasheet HTML 3Page - Digital Core Design DF6811CPU Datasheet HTML 4Page - Digital Core Design DF6811CPU Datasheet HTML 5Page - Digital Core Design DF6811CPU Datasheet HTML 6Page - Digital Core Design DF6811CPU Datasheet HTML 7Page - Digital Core Design  
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All trademarks mentioned in this document
are trademarks of their respective owners.
Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.
http://www.DigitalCoreDesign.com
http://www.dcd.pl
PERFORMANCE
The following table gives a survey about
the Core area and performance in the
ALTERA® devices after Place & Route:
Device
Speed
grade
Logic Cells
Fmax
CYCLONE
-6
1834
58 MHz
STRATIX
-5
1834
60 MHz
MERCURY
-5
1808
61 MHz
APEX II
-7
1849
50 MHz
APEX20KC
-7
1809
46 MHz
APEX20KE
-1
1809
42 MHz
ACEX1K
-1
1785
34 MHz
FLEX10KE
-1
1785
32 MHz
Core performance in ALTERA® devices
IMPROVEMENT
For user the most important is application
speed improvement. The most commonly
used arithmetic functions and theirs improve-
ment are shown in table below. Improvement
was computed as {M68HC11 clock periods}
divided by {DF6811CPU clock periods} re-
quired to execute an identical function. More
details are available in core documentation.
Function
Improve-
ment
8-bit addition (immediate data)
4
8-bit addition (direct addressing)
4
8-bit addition (indirect addressing)
4
8-bit subtraction (immediate data)
4
8-bit subtraction (direct addressing)
4
8-bit subtraction (indirect addressing)
4
16-bit addition (immediate data)
5,3
16-bit addition (direct addressing)
5
16-bit addition (indirect addressing
4,8
16-bit subtraction (immediate data)
5,3
16-bit subtraction (direct addressing)
5
16-bit subtraction (indirect addressing
4,8
Multiplication
10
Fractional division
14,9
Integer division
16.4
DF68XX FAM I LY O V ERVI EW
The main features of each DF68XX family member have been summarized in table below. It gives
a briefly member characterization helping user to select the most suitable IP Core for its application.
User can specify its own peripheral set (including listed below and the others) and requests the core
modifications.
Design
DF6805
4.1
64k
64k
-
7
7
-
-
*
2/2*
1*
*
4
+
*
-
6 700
DF6808
3.2
64k
64k
-
7
7
-
-
*
2/2*
1*
*
4
*
-
8 900
DF6811
4.4
64k
16M
-
20
17
1*
*
5/3*
1*
*
4
*
*
*
12 000
DF6811CPU
4.4
64k
16M
-
3
3
+
1*
*
+
+
+
+
+
+
+
6 500
DF68XX family of High Performance Microcontroller Cores
+ optional
* configurable



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