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Active-HDL automatic simulation mac-

ros

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Floating Point Comparator Unit

ver 2.10

OVERVIEW

The DFPCOMP compares two arguments.

The input numbers format is according to

IEEE-754 standard. DFPCOMP supports

single precision real numbers. Compare op-

eration was pipelined up to 1 level. Input data

are fed every clock cycle. The first result ap-

pears after 1 clock period latency and next

results are available each clock cycle. Full

IEEE-754 unordered compare function is in-

cluded.

APPLI C ATION

Math coprocessors

DSP algorithms

Embedded arithmetic coprocessor

Data processing & control

KEY FEATURES

Full IEEE-754 compliance

Single precision real format support

Simple interface

No programming required

1 level pipeline

Results available at every clock

Fully configurable

Fully synthesizable, static synchronous

design with no internal tri-states

DELIVERABLES

Source code:

VHDL Source Code or/and

VERILOG Source Code or/and

Encrypted, or plain text EDIF netlist

VHDL & VERILOG test bench environ-

ment

NCSim automatic simulation macros

ModelSim automatic simulation macros

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor

and major versions changes

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Delivery the documentation updates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows using IP Core in

single FPGA bitstream and ASIC implemen-

tation. It also permits FPGA prototyping be-

fore ASIC production.