All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, mi-

nor and major versions changes

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Delivery the documentation up-

dates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

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Single Design license for

VHDL, Verilog source code called HDL

Source

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Encrypted, or plain text EDIF called Netlist

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One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

SYMBOL

datai(7:0)

datao(7:0)

irq

rd

we

address(1:0)

scli

sdai

cs

rst

clk

sclhs

sclo

sdao

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

address(1:0)

input

Processor address lines

cs

input

Chip select

we

input

Processor write strobe

rd

input

Processor read strobe

scli

input

I

sdai

input

I

datai(7:0)

input

Processor data bus (input)

datao(7:0)

output

Processor data bus (output)

sclo

output

I

sclhs

output

High-speed clock line (output)

sdao

output

I

irq

output

Processor interrupt line