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SYMBOL

datai(7:0)

datao(7:0)

irq

rd

we

address(2:0)

scli

sdai

cs

rst

clk

sclhs

sclo

sdao

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

address(1:0)

input

Processor address lines

cs

input

Chip select

we

input

Processor write strobe

rd

input

Processor read strobe

scli

input

I

sdai

input

I

datai(7:0)

input

Processor data bus (input)

datao(7:0)

output

Processor data bus (output)

sclo

output

I

sclhs

output

High-speed clock line (output)

sdao

output

I

irq

output

Processor interrupt line

BLOCK DIAGRAM

Figure below shows the DI2CMS IP Core

block diagram.

address(2:0)

datai(7:0)

datao(7:0)

rd

cs

we

rst

clk

irq

CPU

Interface

sdai

sdao

scli

sclo

Input

Filter

Output

Register

Shift

Register

Output

Register

Input

Filter

Timer

Control

Logic

Clock Control

Logic

Send

Data

Receive

Data

Slave

Address

Control

Register

Status

Register

Arbitration

Logic

Output

Register

sclhs

CPU Interface

– Performs the interface func-

tions between DI2CMS internal blocks and

microprocessor. Allows easy connection of the

core to a microprocessor/microcontroller sys-

tem.

Control Logic

– Manages execution of all

commands sent via interface. Synchronizes

internal data flow.

Shift Register

– Controls SDA line, performs

data and address shifts during the data

transmission and reception.

Control Register

– Contains five control bits

transmissions.

Status Register

– Contains seven status bits

DI2CMS core.

Input Filter

– Performs spike filtering.

Clock Control Logic

– Performs clock syn-

chronization, clock generation in master

mode, and clock stretching in slave mode.

Arbitration Logic

– Performs arbitration dur-

ing operations in multi-master systems.

Timer

– Allows operation from a wide range of

the input frequencies. It is programmed by an

user before transmission and can be repro-

grammed to change the SCL frequency.