All trademarks mentioned in this document

are trademarks of their respective owners.

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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http://www.DigitalCoreDesign.com

http://www.dcd.pl

Tests with reference responses

Technical documentation

Installation notes

HDL core specification

Datasheet

Synthesis scripts

Example application

Technical support

IP Core implementation support

3 months maintenance

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Delivery the IP Core updates, minor

and major versions changes

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Delivery the documentation updates

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Phone & email support

LICENSING

Comprehensible and clearly defined licensing

methods without royalty fees make using of

IP Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implemen-

tation.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA

bitstreams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

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○

Single Design license for

VHDL, Verilog source code called HDL

Source

○

Encrypted, or plain text EDIF called Netlist

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One Year license for

Encrypted Netlist only

Unlimited Designs license for

HDL Source

Netlist

Upgrade from

HDL Source to Netlist

Single Design to Unlimited Designs

SYMBOL

datai(7:0)

rd

wr

clk

rst

scli

sdai

sdao

datao(7:0)

PINS DESCRIPTI O N

PIN

TYPE

DESCRIPTION

clk

input

Global clock

rst

input

Global reset

datai(7:0)

input

Data bus from target device

scli

input

I

sdai

input

I

datao(7:0)

output

Data bus to target device

wr

output

Write strobe for target device

rd

output

Read strobe for target device

sdao

output

I

BLOCK DIAGRAM

Figure below shows the DI2CSB IP Core

block diagram.

Target device Interface

– Performs the inter-

face functions between DI2CSB internal

blocks and target device. Allows easy con-

nection of the core to a passive devices e.g.

memory, LCD display, pressure sensors, I/O

devices etc..

datai(7:0)

datao(7:0)

rd

we

rst

clk

Target device

Interface

sdai

sdao

scli

Input

Filter

Output

Register

Shift

Register

Input

Filter

Control

Logic

Synchronization

Logic

Send

Data

Receive

Data

Receive

Data

Own

address

detection