All trademarks mentioned in this document

http://www.DigitalCoreDesign.com

are trademarks of their respective owners.

http://www.dcd.pl

Copyright 1999-2007 DCD – Digital Core Design. All Rights Reserved.

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Bit rates generated 1/4 - 1/512 of system

clock.

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Four transfer formats supported

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Simple interface allows easy connection to

microcontrollers

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Slave operation

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System error detection

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Interrupt generation

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Supports speeds up ¼ of system clock

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Simple interface allows easy connection to

microcontrollers

○

Four transfer formats supported

design with no internal tri-states

DELIVERABLES

♦

Source code:

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VHDL Source Code or/and

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VERILOG Source Code or/and

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Encrypted, or plain text EDIF netlist

♦

VHDL & VERILOG test bench environ-

ment

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Active-HDL automatic simulation macros

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ModelSim automatic simulation macros

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Tests with reference responses

♦

Technical documentation

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Installation notes

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HDL core specification

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Datasheet

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Synthesis scripts

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Example application

♦

Technical support

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IP Core implementation support

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3 months maintenance

●

Delivery the IP Core updates, minor

and major versions changes

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Delivery the documentation updates

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Phone & email support

LICENSI N G

Comprehensible and clearly defined licensing

methods without royalty fees make using of IP

Core easy and simply.

Single Design

license allows use IP Core in

single FPGA bitstream and ASIC implementa-

tion.

Unlimited Designs, One Year

licenses allow

use IP Core in unlimited number of FPGA bit-

streams and ASIC implementations.

In all cases number of IP Core instantiations

within a design, and number of manufactured

chips are unlimited. There is no time restric-

tion except One Year license where time of

use is limited to 12 months.

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VHDL, Verilog source code called HDL

Source

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Encrypted, or plain text EDIF called Netlist

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Encrypted Netlist only

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HDL Source

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Netlist

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HDL Source to Netlist

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Single Design to Unlimited Designs