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Axelite Confidential Materials, do not copy or distribute without written consent.

Rev.1.6 Sep.20, 2019

AX1250ES



APPLICATION CIRCUIT

C3

1

2

3

4

AX1250ES

REFEN

VIN

VOUT

VCNTL

GND

C1

470uF

(Low ESR)

C4

EN

C2

1uF

R1

R2

100K

100K

47uF

VIN=2.5V/1.8V/1.5V

VCNTL=3.3V

RTT

6

RTT=50Ω/33Ω/25Ω

C3=10uF(Ceramic) + 1000uF under the worst case testing condition

ON OFF



APPLICATION INFORMATION

Input Capacitor and Layout Consideration

Place the input bypass capacitor as close as possible to the AX1250ES. A low ESR

capacitor larger than 470uF is recommended for the input capacitor. Use short and wide

traces to minimize parasitic resistance and inductance. Inappropriate layout may result in

large parasitic inductance and cause undesired oscillation between AX1250ES and the

preceding power converter.

Consideration while designs the resistance of voltage divider

Make sure the sinking current capability of pull-down NMOS if the lower resistance

was chosen so that the voltage on VREFEN is below 0.2V. In addition, the capacitor and

voltage divider form the low pass filter. There are two reasons doing this design; one is

for output voltage soft-start while another is for noise immunity.

R1

R2

R3

R4

R5

R6

R7

R8

R9

R(2N)

R(2N+1)

R0

BUS(2N)

BUS(2N+1)

BUS(9)

BUS(8)

BUS(7)

BUS(6)

BUS(5)

BUS(4)

BUS(3)

BUS(2)

BUS(1)

BUS(0)

Terminator Resistor

AX1250ES

AX1250ES

VOUT

VOUT

REFEN