DSP56321 datasheet(33/84 Pages) FREESCALE

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AC Electrical Characteristics

DSP56321 Technical Data, Rev. 11

Freescale Semiconductor

2-13

2.4.5.2 Asynchronous Bus Arbitration Timings

Figure 2-11.

SRAM Write Access

Table 2-9.

Asynchronous Bus Timings

No.

Characteristics

Expression

200 MHz

220 MHz

240 MHz

275 Mhz

Uni

Min

Max

Min

Max

Min

Max

Min

Max

250

BB assertion window from BG input

deassertion.

2.5

× Tc + 5

—

17.5

—

16.4

—

15.4

—

14.1

251

Delay from BB assertion to BG assertion

× Tc + 5

—

14.1

—

13.3

—

12.27

—

Notes:

Bit 13 in the Operating Mode Register must be set to enable Asynchronous Arbitration mode.

To guarantee timings 250 and 251, it is recommended that you assert non-overlapping BG inputs to different DSP56300

devices (on the same bus), as shown in Figure 2-12, where BG1 is the BG signal for one DSP56300 device while BG2 is the

BG signal for a second DSP56300 device.

A[0–17]

Data

Out

D[0–23]

AA[0–3]

100

102

101

107

114

108

109

103

118

119

Note: Address lines A[0–17] hold their state after a

read or write operation. AA[0–3] do not hold their

state after a read or write operation.

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