TMP88CS38 datasheet(58/226 Pages) TOSHIBA

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TMP88CS38/CM38A/CP38A

2007-09-12

88CS38-58

Example: Sets the watchdog timer detection time to 2

21/fc [s] and resets the CPU malfunction.

(WDTCR2), 4EH

; Clears the binary counters

(WDTCR1), 00001101B

; WDTT

← 10, WDTOUT ← 1

(WDTCR2), 4EH

; Clears the binary counters

(always clear immediately before and after changing WDTT)

(WDTCR2), 4EH

; Clears the binary counters

(WDTCR2), 4EH

; Clears the binary counters

Watchdog Timer Register 1

WDTCR1

(00034H)

WDTEN

WDTT

WDTOUT

(Initial value: **** 1001)

WDTEN

Watchdog timer

enable/disable

0: Disable (It is necessary to write the disable code to

WDTCR2)

1: Enable

NORMAL mode

DV1CK

= 0

DV1CK

= 1

25 /fc

26/fc

23/fc

24/fc

21/fc

22/fc

WDTT

Watchdog timer

detection time [s]

19/fc

20/fc

WDTOUT

Watchdog timer

output select

0: Interrupt request

1: Reset output

Write

only

Note 1:

WDTOUT cannot be set to “1” by program after clearing WDTOUT to “0”.

Note 2:

fc: High-frequency clock [Hz], *: Don’t care

Note 3:

WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions.

Note 4:

The watchdog timer must be disabled or the counter must be cleared immediately before entering to the

STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing

the STOP mode.

Note 5:

Just right before disabling the watchdog timer, disable the acceptance of interrupts (DI) and clear the

watchdog timer.

If the watchdog timer is disabled under conditions other than the above, the proper operation cannot be

guaranteed.

Watchdog Timer Register 2

WDTCR2

(00035H)

(Initial value: **** ****)

WDTCR2

Watchdog timer control

code write register

4EH: Watchdog timer binary counter clear (Clear code)

B1H: Watchdog timer disable (Disable code)

Others: Invalid

Write

only

Note 1:

The disable code is invalid unless written when WDTEN

= 0.

Note 2:

*: Don’t care

Note 3:

The binary counter of the watchdog timer must not be cleared by the interrupt task.

Note 4:

Clears the binary counter does not clear the source clock.

It is recommended that the time to clear is set to 3/4 of the detecting time.

Note 5:

The watchdog timer counter must be disabled by writing the disable code (B1H) to WDRCR2 after writing

WDTCR2 to. “4EH”.

Figure 2.4.2 Watchdog Timer Control Registers

Within 3/4 of WDT

detection time

Within 3/4 of WDT

detection time

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