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ADPL40502ACPZ-3.3-R7 데이터시트(PDF) 6 Page - Analog Devices |
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ADPL40502ACPZ-3.3-R7 데이터시트(HTML) 6 Page - Analog Devices |
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6 / 17 page ![]() Data Sheet ADPL40502 analog.com Rev. 0 6 of 17 Therefore, ΨJB thermal paths include convection from the top of the package as well as radiation from the package, factors that make ΨJB more useful in real-world applications. To calculate the maximum TJ from the board temperature (TB) and PD, use the following equation: TJ = TB + (PD × ΨJB) See JESD51-8 and JESD51-12 for more detailed information about ΨJB. Thermal Resistance θJA and ΨJB are specified for the worst-case conditions, that is, a device soldered in a circuit board for surface-mount packages. Table 4. Thermal Resistance Package Type θJA ΨJB Unit 5-Lead TSOT (UJ-5) 170 43 °C/W 6-Lead LFCSP (CP-6-3) 63.6 28.3 °C/W ESD Caution ESD (electrostatic discharge) sensitive device. Charged devices and circuit boards can discharge without detection. Although this product features patented or proprietary protection circuitry, damage may occur on devices subjected to high energy ESD. Therefore, proper ESD precautions should be taken to avoid performance degradation or loss of functionality. |
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