NXP Semiconductors

SL3S1005

UCODE 9xm

Pad height uniformity

– within a die

max. 2 µm

– within a wafer

max. 4 µm

Pad flatness

max. 3 µm

Pad size

– RF1, RF2 (max. details see wafer layout)

176 µm × 361.5 µm

– TP1, TP2 (max. details see wafer layout)

160 µm × 70.5 µm

Pad size variation

± 5 µm

Table 3. 12-inch specification, plasma diced...continued

8.1.2 Fail die identification

No ink dots are applied to the wafer.

Electronic wafer mapping (SECS II format) covers the electrical test results and additionally the results of

mechanical/visual inspection.

See [3].

8.1.3 Map file distribution

See [3].

SL3S1005

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Product data sheet

Rev. 3.1 — 12 February 2025

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