TMP86FS49AIUG datasheet(215/296 Pages) TOSHIBA

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Page 199

TMP86FS49AIUG

16.5.1 Acknowledgement mode specification

16.5.1.1 Acknowledgment mode (ACK = “1”)

To set the device as an acknowledgment mode, the ACK (Bit4 in SBICRA) should be set to “1”. When

a serial bus interface circuit is a master mode, an additional clock pulse is generated for an acknowledge

signal. In a slave mode, a clock is counted for the acknowledge signal.

In the master transmitter mode, the SDA pin is released in order to receive an acknowledge signal from

the receiver during additional clock pulse cycle. In the master receiver mode, the SDA pin is set to low

level generation an acknowledge signal during additional clock pulse cycle.

In a slave mode, when a received slave address matches to a slave address which is set to the I2CAR or

when a “GENERAL CALL” is received, the SDA pin is set to low level generating an acknowledge sig-

nal. After the matching of slave address or the detection of “GENERAL CALL”, in the transmitter, the

SDA pin is released in order to receive an acknowledge signal from the receiver during additional clock

pulse cycle. In a receiver, the SDA pin is set to low level generation an acknowledge signal during addi-

tional clock pulse cycle after the matching of slave address or the detection of “GENERAL CALL”

The Table 16-1 shows the SCL and SDA pins status in acknowledgment mode.

16.5.1.2 Non-acknowledgment mode (ACK = “0”)

To set the device as a non-acknowledgement mode, the ACK (Bit4 in SBICRA) should be cleared to

“0”.

MST

Master/slave selection status

monitor

Slave

Read

only

Master

TRX

Transmitter/receiver selection

status monitor

Receiver

Transmitter

Bus status monitor

Bus free

Bus busy

Interrupt service requests sta-

tus monitor

Requesting interrupt service

Releasing interrupt service request

Arbitration lost detection monitor

–

Arbitration lost detected

AAS

Slave address match detection

monitor

Detect slave address match or "GENERAL CALL"

AD0

"GENERAL CALL" detection

monitor

Detect "GENERAL CALL"

LRB

Last received bit monitor

Last receive bit is "0"

Last receiv bit is "1"

Table 16-1 SCL and SDA Pins Status in Acknowledgement Mode

Mode

Transmitter

Receiver

Master

SCL

An additional clock pulse is generated.

SDA

Released in order to receive

an acknowledge signal.

Set to low level generating an

acknowledge signal

Slave

SCL

A clock is counted for the acknowledge signal.

SDA

When slave address matches

or a general call is detected

–

Set to low level generating an

acknowledge signal.

After matching of slave

address or general call

Released in order to receive

an acknowledge signal.

Set to low level generating an

acknowledge signal.

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