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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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TMP86FS49AIUG 데이터시트(PDF) 280 Page - Toshiba Semiconductor |
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TMP86FS49AIUG 데이터시트(HTML) 280 Page - Toshiba Semiconductor |
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280 / 296 page  Page 264 21. Input/Output Circuit 21.1 Control pins TMP86FS49AIUG 21.2 Input/Output Ports Port I/O Input/Output Circuitry Remarks P1 I/O Tri-state I/O Hysteresis input R = 100 Ω (typ.) P3 I/O Sink open drain output High current output R = 100 Ω (typ.) P2 I/O Sink open drain output Hysteresis input R = 100 Ω (typ.) P5 I/O Sink open drain output High current output Hysteresis input R = 100 Ω (typ.) P0 P4 I/O Sink open drain output or C-MOS output Hysteresis input R = 100 Ω (typ.) Initial "High-Z" Disable Data output Pin input VDD R R Initial "High-Z" Data output Output latch input Pin input VDD R Initial "High-Z" Data output Output latch input Pin input R Initial "High-Z" Data output Output latch input Pin input P-ch control Disable VDD R Initial "High-Z" Output latch input Pin input (Control input) Data output |
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