KSZ9567R_V01 datasheet(60/233 Pages) MICROCHIP

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KSZ9567R

DS00002329E-page 60

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The MIIM Interface can operate up to a maximum clock speed of 5MHz. Access is limited to only the registers in the

PHY blocks of ports 1 through 5. Table 4-26 summarizes the MII management interface frame format.

The MIIM PHY address to PHY port mapping is as follows:

• PHY Address 1h to PHY port 1

• PHY Address 2h to PHY port 2

• PHY Address 3h to PHY port 3

• PHY Address 4h to PHY port 4

• PHY Address 5h to PHY port 5

The MIIM register address space consists of two distinct areas.

• Standard MIIM Registers (Direct)

• MDIO Manageable Device (MMD) Registers (Indirect)

4.11.3.1

Standard MIIM Registers (Direct)

Standard registers provide direct read/write access to a 32-register address space, as defined in Clause 22 of the IEEE

802.3 Specification. Within this address space, the first 16 registers (Registers 0h to Fh) are defined according to the

IEEE specification, while the remaining 16 registers (Registers 10h to 1Fh) are defined specific to the PHY vendor.

The KSZ9567R supports the standard registers listed in Table 4-27 for each PHY port. Each 16-bit MIIM Standard Reg-

ister Address maps to two corresponding 8-bit Port N Register Addresses. The register bit map and description are

located at the 8-bit Port N Register Addresses.

TABLE 4-26:

MII MANAGEMENT INTERFACE FRAME FORMAT

Operation

Mode

Preamble

(32-bit)

Start of

Frame

(2-bit)

Operation

Code

(2-bit)

PHY

Address

(5-bit)

Address

(5-bit)

Turn

Around

(2-bit)

Data

(16-bit)

Idle

Read

All 1s

A[4:0]

Reg[4:0]

D[15:0]

Write

All 1s

A[4:0]

Reg[4:0]

D[15:0]

TABLE 4-27:

STANDARD MIIM REGISTERS

MIIM Standard

(hex)

Port N

(hex)

Description

IEEE-Defined Registers

0xN100 - 0xN101

PHY Basic Control Register

0xN102 - 0xN103

PHY Basic Status Register

0xN104 - 0xN105

PHY ID High Register

0xN106 - 0xN107

PHY ID Low Register

0xN108 - 0xN109

PHY Auto-Negotiation Advertisement Register

0xN10A - 0xN10B

PHY Auto-Negotiation Link Partner Ability Register

0xN10C - 0xN10D

PHY Auto-Negotiation Expansion Status Register

0xN10E - 0xN10F

PHY Auto-Negotiation Next Page Register

0xN110 - 0xN111

PHY Auto-Negotiation Link Partner Next Page Ability Register

0xN112 - 0xN113

PHY 1000BASE-T Control Register

0xN114 - 0xN115

PHY 1000BASE-T Status Register

Bh-Ch

RESERVED

0xN11A - 0xN11B

PHY MMD Setup Register

0xN11C - 0xN11D

PHY MMD Data Register

0xN11E - 0xN11F

PHY Extended Status Register

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