KSZ9567R_V01 datasheet(171/233 Pages) MICROCHIP

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DS00002329E-page 171

KSZ9567R

5.2.7.2

Port Priority Control Register

To achieve the desired functionality, do not set more than one bit at a time in this register.

5.2.7.3

Port Ingress MAC Control Register

Address:

0xN801

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

Highest Priority

1 = Highest priority selected

0 = Highest priority not selected

R/W

OR’ed Priority

1 = All available priority OR’ed

0 = All available priority not OR’ed

R/W

RESERVED

MAC Address Priority Classification

1 = Enable MAC address priority classification for ingress packets on port

0 = Disable MAC address classification

R/W

VLAN Priority Classification

1 = Enable VLAN priority classification for ingress packets on port

0 = Disabled VLAN classification

R/W

802.1p Priority Classification

1 = Enable 802.1p priority classification for ingress packets on port

0 = Disable 802.1p priority classification

R/W

Diffserv Priority Classification

1 = Enable Diffserv priority classification for ingress packets on port

0 = Disable Diffserv priority classification

R/W

ACL Priority Classification

1 = Enable ACL priority classification for ingress packets on port

0 = Disable ACL priority classification

R/W

Address:

0xN802

Port N: 1-7

Size:

8 bits

Bits

Description

Type

Default

User Priority Ceiling

1 = If a packet’s “user priority field” is greater than the “user priority field” in

the port default tag register, replace the packet’s user priority field with the

user priority field in the port default tag from the Port Default Tag 0 Register.

0 = Do not replace the user priority field at this port.

R/W

6:5

RESERVED

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