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TC74ACT02FN 데이터시트(PDF) 3 Page - Toshiba Semiconductor

부품명 TC74ACT02FN
상세설명  CMOS Digital Integrated Circuit Silicon Monolithic Quad 2-Input NOR Gate
PDF  8 Pages
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제조업체  TOSHIBA [Toshiba Semiconductor]
홈페이지  http://www.semicon.toshiba.co.jp/eng
Logo TOSHIBA - Toshiba Semiconductor

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TC74ACT02P/F/FN/FT
2007-10-01
3
Operating Ranges (Note)
Characteristics
Symbol
Rating
Unit
Supply voltage
VCC
4.5 to 5.5
V
Input voltage
VIN
0 to VCC
V
Output voltage
VOUT
0 to VCC
V
Operating temperature
Topr
−40 to 85
°C
Input rise and fall time
dt/dV
0 to 10
ns/V
Note:
The operating ranges must be maintained to ensure the normal operation of the device.
Unused inputs must be tied to either VCC or GND.
Electrical Characteristics
DC Characteristics
Test Condition
Ta = 25°C
Ta =
−40 to 85°C
Characteristics
Symbol
VCC
(V)
Min
Typ.
Max
Min
Max
Unit
High-level input
voltage
VIH
4.5
to
5.5
2.0
2.0
V
Low-level input
voltage
VIL
4.5
to
5.5
0.8
0.8
V
High-level output
voltage
VOH
VIN
= VIL
IOH = −50 μA
IOH = −24 mA
IOH = −75 mA (Note)
4.5
4.5
5.5
4.4
3.94
4.5
4.4
3.80
3.85
V
Low-level output
voltage
VOL
VIN
= VIH or
VIL
IOL = 50 μA
IOL = 24 mA
IOL = 75 mA
(Note)
4.5
4.5
5.5
0.0
0.1
0.36
0.1
0.44
1.65
V
Input leakage
current
IIN
VIN = VCC or GND
5.5
±0.1
±1.0
μA
ICC
VIN = VCC or GND
5.5
4.0
40.0
μA
Quiescent supply
current
IC
Per input: VIN = 3.4 V
Other input: VCC or GND
5.5
1.35
1.5
mA
Note:
This spec indicates the capability of driving 50 Ω transmission lines.
One output should be tested at a time for a 10 ms maximum duration.
AC Characteristics (CL = 50 pF, RL = 500 Ω, input: tr = tf = 3 ns)
Test Condition
Ta = 25°C
Ta =
−40 to 85°C
Characteristics
Symbol
VCC (V)
Min
Typ.
Max
Min
Max
Unit
Propagation delay
time
tpLH
tpHL
5.0 ± 0.5
5.3
8.3
1.0
9.5
ns
Input capacitance
CIN
5
10
10
pF
Power dissipation
capacitance
CPD
(Note)
22
pF
Note:
CPD is defined as the value of the internal equivalent capacitance which is calculated from the operating
current consumption without load.
Average operating current can be obtained by the equation:
ICC (opr) = CPD·VCC·fIN + ICC/4 (per gate)



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