MCP3460R datasheet(29/103 Pages) MICROCHIP

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DS20006975A page 29

MCP3460R

4.0

TERMINOLOGY AND

FORMULAS

This section defines the terms and formulas used

throughout this document. The following terms are

defined:

• MCLK – Main Clock

• AMCLK – Analog Main Clock

• DMCLK – Digital Main Clock

• DRCLK – Data Rate Clock

• OSR – Oversampling Ratio

• Offset Error

• Gain Error

• Integral Nonlinearity Error (INL)

• Signal-to-Noise Ratio (SNR)

• Signal-to-Noise and Distortion Ratio (SINAD)

• Total Harmonic Distortion (THD)

• Spurious-Free Dynamic Range (SFDR)

• MCP3460R Delta-Sigma Architecture

• Power Supply Rejection Ratio (PSRR)

• Common Mode Rejection Ratio (CMRR)

• Digital Pins Output Current Consumption

FIGURE 4-1:

System Clock Details.

4.1

MCLK – Main Clock

This is the main clock frequency at the MCLK input pin

when an external clock source is selected or internal

clock frequency when the internal clock is selected.

4.2

AMCLK – Analog Main Clock

This is the clock frequency that is present on the analog

portion of the device after prescaling has occurred via

the PRE[1:0] bits.

EQUATION 4-1:

ANALOG MAIN CLOCK

4.3

DMCLK – Digital Main Clock

This is the clock frequency that is present on the digital

portion of the device. This is also the sampling frequency

or the rate at which the modulator outputs are refreshed.

Each period of this clock corresponds to one sample and

one modulator output. See Equation 4-2.

EQUATION 4-2:

DIGITAL MAIN CLOCK

4.4

DRCLK – Data Rate Clock

This is the output data rate in Continuous mode or the

rate at which the ADC outputs new data. Any new data

are signaled by a data ready pulse on the IRQ pin.

This data rate depends on the OSR and the prescaler,

as shown in Equation 4-3.

EQUATION 4-3:

DATA RATE

Since this is the output data rate and since the

decimation filter is a sinc (or notch) filter, there is a

notch in the filter transfer function at each integer

multiple of this rate.

MCLK

Pad

1/OSR

Internal Oscillator

MCLK

Multiplexer

OU T

PRESCALE

1/4

AMCLK

DMCLK

DRCLK

Clock Divider

OSR[3:0]

PRE[1:0]

CLK_SEL[1]

AMCLKOUT

CLK_SEL[1] = 0

CLK_SEL[1:0] = 11

AMCLK

MCLK

Prescale

-----------------------

DMCLK

AMCLK

---------------------

MCLK

4 Prescale



--------------------------------

DRCLK

DMCLK

OSR

----------------------

AMCLK

4OSR



---------------------

MCLK

4 OSR Prescale



---------------------------------------------------

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