MCP3919B datasheet(21/81 Pages) MICROCHIP

21 / 81 page

 2025 Microchip Technology Inc. and its subsidiaries

DS20006995A-page 21

MCP3919B

a WRITE command. Toggling SDI after a READ or

WRITE command, or when CS is logic high has no

effect.

This input is Schmitt triggered.

In Two-Wire Interface mode, this is the OSR1 logic

select input pin (see Section 7.0 “Two-Wire Serial

Interface Description” for the logic input table for

OSR0 and OSR1). The pin state is latched when the

mode changes to Two-Wire Interface mode and is

relatched at each Watchdog Timer Reset.

3.14

Master Reset/OSR0 Logic Input

(RESET/OSR0)

In SPI mode, this pin is active-low and places the entire

chip in a Reset state when active.

When RESET is logic low, all registers are reset to their

default value, no communication can take place and no

clock is distributed inside the part, except in the input

structure if MCLK is applied (if MCLK is Idle, then no

clock is distributed). This state is equivalent to a

Power-on Reset (POR) state.

Since the default state of the ADCs is on, the analog

power consumption when RESET is logic low is equiv-

alent to when RESET is logic high. Only the digital

power consumption is largely reduced because this

current consumption is essentially dynamic and is

reduced drastically when there is no clock running.

All the analog biases are enabled during a Reset, so

that the part is fully operational 2-MCLK periods just

after a RESET rising edge. However, after a POR or

Master/Hard Reset event, the part may require a start-

up time to allow settling of the input structure and

internal circuity before generating reliable and accurate

results.

This input is Schmitt-triggered.

In Two-Wire Interface mode, this is the OSR0 logic

select pin (see Section 7.0 “Two-Wire Serial Inter-

face Description” for the logic input table for OSR0

and OSR1). The pin state is latched when the mode

changes to Two-Wire Interface mode and is relatched

at each Watchdog Timer Reset.

3.15

Digital Power Supply (DVDD)

DVDD is the power supply voltage for the digital circuitry

within the MCP3919B. It is distributed on several pins

(pins 12 and 24 in the QFN package, one pin only in the

SSOP package). For optimal performance, it is

recommended to connect these pins together using a

star connection and to connect appropriate bypass

capacitors (typically a 10 µF in parallel with a 0.1 µF

ceramic). Maintain DVDD between 2.7V and 3.6V for

specified operation.

At least one of these pins needs to be properly

connected to ensure proper functionality of the device.

All of these pins need to be properly connected to

ensure optimal performance of the device. If any of

these pins are left floating, the accuracy and noise

specifications are not ensured.

3.16

Exposed Thermal Pad

This pin must be connected to AGND or left floating for

proper operation. Connecting it to AGND is preferable for

lowest noise performance and best thermal behavior.

MCP3919B 데이터시트(PDF) 21 Page - Microchip Technology

MCP3919B 데이터시트(HTML) 21 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81

데이터시트 다운로드

링크 URL