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AD4058BCPZ-R2 데이터시트(PDF) 37 Page - Analog Devices

부품명 AD4058BCPZ-R2
상세설명  Compact, Low Power, 16-Bit, 2 MSPS/500 kSPS Easy Drive SAR ADC
PDF  66 Pages
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제조업체  AD [Analog Devices]
홈페이지  http://www.analog.com
Logo AD - Analog Devices

AD4058BCPZ-R2 데이터시트(HTML) 37 Page - Analog Devices

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Data Sheet
AD4052/AD4058
MODES OF OPERATION
analog.com
Rev. B | 37 of 66
Autonomous Mode Diagrams
Figure 63. Autonomous Mode Example Connection Diagram
Figure 64. Trigger Mode Timing Diagram
SLEEP MODE
In sleep mode, the AD4052/AD4058 power down all functional
blocks, except the digital interface, to achieve an ultra-low power
consumption of 430 nW for extended periods of idle time (see
Table 1). Set the POWER_MODE bit field in the DEVICE_CONFIG
register to 2'h3 to put the AD4052/AD4058 into sleep mode.
The internal LDO regulator is powered down and stops supplying
the +1.8 V CLDO supply while in sleep mode. This feature powers
down the ADC core and most other functional blocks. The digital
interface remains active, so the digital host can rewrite the POW-
ER_MODE bit field to 2'h0 to exit sleep mode and power up the
device. When the device exits sleep mode, it enters configuration
mode. The configuration register states persist, so the digital host
does not need to reprogram the device configuration after exiting
sleep mode.



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