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Modifications reserved | Data subject to change without notice

Document number: BST-BMA456-DS000-08

Revision_3.5_032025

Non-Volatile Memory

The registers NV_CONF and OFFSET_0 to OFFSET_2 have an NVM backup which are accessible

by the user.

The content of the NVM is loaded to the image registers after a reset (either POR or softreset). As

long as the image update is in progress, STATUS.cmd_rdy is 0b0, otherwise it is 0b1.

The image registers can be read and written like any other register.

Writing to the NVM is a 4-step procedure:

1. Set PWR_CONF.adv_power_save = 0b0

2. Write the new contents to the image registers.

3. Write 0b1 to bit NVM_CONF.nvm_prog_en in order to unlock the NVM.

4. Write nvm_prog to the CMD register to trigger the write process.

Writing to the NVM always renews the entire NVM contents. It is possible to check the write status by

reading STATUS.cmd_rdy. While STATUS.cmd_rdy = 0b0, the write process is still in progress; when

STATUS.cmd_rdy = 0b1, writing is completed. An NVM write cycle can only be initiated, if

PWR_CONF.adv_power_save = 0b0.

Until boot phase is finished (after POR or softreset), the serial interface is not operational. The NVM

shadow registers must not be accessed during an ongoing NVM command (initiated through the

As long as an NVM read (during sensor boot and soft reset) or an NVM write is ongoing, writes to

sensor registers are discarded, reads return the Register STATUS independent of the read address.

Soft-Reset

A softreset can be initiated at any time by writing the command softreset (0xB6) to register CMD. The

softreset performs a fundamental reset to the device which is largely equivalent to a power cycle.

Following a delay, all user configuration settings are overwritten with their default state (setting stored

in the NVM) wherever applicable. This command is functional in all operation modes but must not be

performed while NVM writing operation is in progress.

Soft reset timing:

In I2C mode, the rising edge of the SCL line for the ACK bit of the soft reset transfer determines the

reception of soft reset. The execution of the soft rest is delayed by 0.5 – 1us if the sensor is not in

advanced power save mode i.e. PWR_CONF.adv_power_save=0b0.

The execution of the soft reset causes that the SDA line to be released immediately by the device,

independent of the state of the SCL line.

If the host requires an explicit I2C ACK for the soft reset (i.e. SDA line remains low while the SCL line

is high) the host must put the sensor in advance power save mode

(PWR_CONF.adv_power_save=0b1), disable the sensor (PWR_CTRL.acc_en=0b0) and the auxillary

interface (PWR_CTRL.aux_en=0b0) before issuing a soft reset.

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