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전자부품 데이터시트 검색엔진 |
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전자부품 데이터시트 검색엔진 |
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AX88196BLF 데이터시트(PDF) 75 Page - ASIX Electronics Corporation |
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AX88196BLF 데이터시트(HTML) 75 Page - ASIX Electronics Corporation |
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75 / 86 page  ASIX ELECTRONICS CORPORATION 75 AX88196BLF 7.4.6 MII Timing Tth Tts Ttcl k Ttcl Ttcl k Ttcl Ttch Ttch TXCLK TXEN / TXD[3:0] Symbol Description Min Typ. Max Units Ttclk TXCLK clock cycle time *1 - 40.0 - ns Ttch TXCLK clock high time *2 - 20.0 - ns Ttcl TXCLK clock low time *2 - 20.0 - ns Tts TXD [3:0], TXEN setup to rising TXCLK 30 - - ns Tth TXD [3:0], TXEN hold from rising TXCLK 4 - - ns Trh Trs Trclk Trcl Trclk Trcl Trch Trch RXCLK RXDV / RXD[3:0] Symbol Description Min Typ. Max Units Trclk RXCLK clock cycle time *1 - 40.0 - ns Trch RXCLK clock high time *2 - 20.0 - ns Trcl RXCLK clock low time *2 - 20.0 - ns Trs RXD [3:0], RXDV setup to rising RXCLK 4 - - ns Trh RXD [3:0], RXDV hold from rising TXCLK 4 - - ns *1: For 10Mbps, the typical value of Ttclk and Trclk shall scale to 400ns. *2: For 10Mbps, the typical value of Ttch, Ttcl, Trch, and Trcl shall scale to 200ns. |
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