AD4056BCPZ-R2 datasheet(11/67 Pages) AD

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Data Sheet

AD4050/AD4056

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. A | 11 of 67

Figure 4. AD4050/AD4056 LFCSP Pin Configuration

Figure 5. AD4050/AD4056 WLCSP Pin Configuration

Table 10. AD4050/AD4056 LFCSP and WLCSP Pin Function Descriptions

LFCSP Pin No.

WLCSP Pin No. Mnemonic

Type

Description

GP1

General Purpose Output 1. The GP1 pin is a digital output that can be configured as multiple

device interrupt signals. See the Interrupts and Control Signals section.

IN−

Negative Analog Input. See the Analog Inputs section.

IN+

Positive Analog Input. See the Analog Inputs section.

REF

Reference Input. Decouple the REF pin with a 2.2 μF capacitor to GND. See the Voltage

Reference section.

C1, C4, D2

GND

Power Supply Ground.

VDD

Analog Power Supply. Decouple the VDD pin with a 1 μF capacitor to GND. The VDD pin is also

the input to the +1.8 V internal LDO regulator that supplies the CLDO pin supply voltage. See

the Power Supplies section.

CLDO

ADC Core Power Supply. The CLDO pin is powered by the +1.8 V internal LDO regulator.

Decouple the CLDO pin with a 1 μF capacitor to GND. See the Power Supplies section.

VIO

Logic Voltage Supply. The VIO pin sets the logic voltage levels for digital inputs and digital

outputs. Decouple the VIO pin with a 1 μF capacitor to GND. See the Power Supplies section.

Chip Select Input (Active Low). See the Serial Interface section.

SDO

Serial Data Output. See the Serial Interface section.

SCLK

Serial Data Clock Input. See the Serial Interface section.

SDI

Serial Data Input. See the Serial Interface section.

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