ADE9112 datasheet(10/55 Pages) AD

10 / 55 page

Data Sheet

ADE9103/ADE9112/ADE9113

SPECIFICATIONS

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Rev. A | 10 of 55

TIMING CHARACTERISTICS

VDD = 3.3 V ± 10%, AGND = 0 V, DGND = 0 V, on-chip reference, XTALIN = 16.384 MHz, and TMIN to TMAX = −40°C to +125°C, unless

otherwise noted.

Table 3. SPI Interface Timing Parameters

Parameter1

Symbol

Min

Max

Unit

CS to SCLK Positive Edge

tSS

SCLK Frequency

fSCLK

20,000

kHz

SCLK Low Pulse Width

tSL

SCLK High Pulse Width

tSH

Data Output Valid After CS Edge

tDAVFB

Subsequent Data Output Valid After SCLK Edge

tDAVSB

Data Input Setup Time Before SCLK Edge

tDSU

Data Input Hold Time After SCLK Edge

tDHD

Data Output Fall Time

tDF

Data Output Rise Time

tDR

SCLK Rise Time

tSR

SCLK Fall Time

tSF

MISO Disable After CS Rising Edge

tDIS

CS High After SCLK Edge

tSFS

CS High Time Between SPI Transactions

tCH

Nonisolated (NONISO) Side

400

Isolated (ISO) Side

10,000

1 Specifications guaranteed by design and characterization and not subject to production test.

Timing Diagrams

Figure 5. SPI Timing, CPOL = 1 and CHPA = 1

Figure 6. Load Circuit for Timing Specifications

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